1. Field of the Invention
This invention relates to a circuit arrangement for synchronizing the successive, low sampling rate samples of a data stream converted from a high rate to the low sampling rate and represented as a sequence of samples of a signal with a first synchronizing signal contained in the high sampling rate data stream. Such a synchronizing circuit comprises memory which can be cyclically written and read in an equidirectional address sequence. The memory can receive write address signals for writing the samples of the high sampling rate data stream from a write address counter which counts periods of a first sampling clock signal having the high sampling rate, and read address signals for reading the samples of the equally high sampling rate data stream from a combination circuit in which the read address signals can be generated from an additive combination of the write address signals with a difference address signal. The circuit also includes an arrangement for forming the difference address signal.
2. Description of the Related Art
A circuit arrangement in which a digital television signal present as a sequence of samples at a first sampling frequency can be converted into a sequence of samples at a second sampling frequency is known from EP-PS 0 080 712. This document proposes measures for obtaining the samples of an output signal by interpolation of the samples of an input signal. This document does not give any indication about synchronization of the samples of the output signal by means of a predetermined synchronizing signal.
Synchronization of the samples is necessary, particularly with a conversion of time-discrete television signals, i.e. signals which are present as a sequence of samples having a given sampling rate and constitute a data stream, into another sampling rate. Such a synchronization may also be important for signals other than the aforesaid television signals. A particular application is a conversion from a high to a low sampling rate. For example, in horizontally coupled television systems, it should be ensured that the reference for the start of the picture in each line is at a predetermined position independent of the sampling rate.
It is feasible to align the start of the picture in each line at the predetermined position by means of an analog or digital phase control of the sampling clock, particularly the clock having the low sampling rate, in dependence upon a horizontal synchronizing signal. However, this is very elaborate and does not lead to the envisaged object in many cases.
A circuit arrangement for digital, line-frequency coarse correction of time base errors upon playback of a video recording on a video recorder and upon display of this video recording on a display screen is known from the monograph by B Morgenstern, "Technik der magnetischen Videosignalaufzeichnung", Teubner Verlag 1985, section 5.5.4.4, pp. 111 to 113. This arrangement comprises a random access memory in which consecutive data words consisting of data of three pixels each are written. This memory is organized in such a way that the values of the pixels are cyclically written from the tape with an increasing address sequence. The time error correction is achieved in that the time base error is converted into an address difference. After a pixel has been written into the memory, another pixel is immediately read whose address results from that of the pixel which has just been written into the memory and has been changed by the address difference, the address difference or the difference address being determined by a time error detector. The write address sequence is generated by a write address counter which is cyclically clocked at a third of the sampling frequency. The time error detector, which receives the horizontal synchronizing signal from the tape and a horizontal synchronizing reference, determines the time error as a number of periods of the clock frequency of the write address counter and converts it into the address difference which is processed, during writing, in a subtracter stage.
The description of this circuit arrangement does not give any indication about synchronization at a sampling rate conversion.